set associative cache - A compromise between a direct mapped cache and a fully associative cache where each address is mapped to a certain set of cache locations. The address space is divided into blocks of 2^m bytes (the cache line size), discarding the bottom m address bits. An "n-way set associative" cache with S sets has n cache locations in each set. Block b is mapped to set "b mod S" and may be stored in any of the n locations in that set with its upper address bits as a tag. To determine whether block b is in the cache, set "b mod S" is searched associatively for the tag.A direct mapped cache could be described as "one-way set associative", i.e. one location in each set whereas a fully associative cache is N-way associative (where N is the total number of blocks in the cache). Performance studies have shown that it is generally more effective to increase the number of entries rather than associativity and that 2- to 16-way set associative caches perform almost as well as fully associative caches at little extra cost over direct mapping.
source : http://encyclopedia2.thefreedictionary.com/set+associative+cache
Showing posts with label hardware. Show all posts
Showing posts with label hardware. Show all posts
Sunday, March 1, 2009
Wednesday, May 28, 2008
What is the purpose of Wi-Fi ad-hoc mode? Why would I use it?
The 802.11 standard defines two modes of operation: Infrastructure mode, where all stations communicate through an access point, and ad-hoc mode, where stations communicate directly without the help of an intermediary. Ad-hoc mode can be useful for temporary peer-to-peer applications, such as when two laptop users want to exchange files over Wi-Fi.
Most businesses discourage use of ad-hoc mode because they prefer to enforce corporate security policy at the access point and gateway or switch connected to the access point. Users that communicate directly over ad-hoc mode essentially bypass those security measures. Ad-hoc mode can even be used as an attack method. For example, a Windows XP PC that previously associated to an access point with a given name (SSID) can be tricked into automatically re-associating in Ad-hoc mode to an attacker's laptop that advertises that SSID. You avoid this attack by configuring XP (or any other wireless client software) to associate to preferred SSIDs in infrastructure mode only.
On the other hand, several vendors are now using ad-hoc mode as the foundation for building wireless mesh networks. Mesh networks have many applications, including outdoor metropolitan networks and mobile ad-hoc networks (MANETs). To learn more about Ad-hoc mode and its use in mesh networks, visit this NIST resource page. A standard for mesh networks is now under development, designated IEEE 802.11s.
In short, ad-hoc mode has many constructive uses, but unless you have a specific reason for enabling, your safest best today is to disable ad-hoc mode to prevent unwanted or risky associations.
source
What is bridge in network world
In telecommunication networks, a bridge is a product that connects a local area network (LAN) to another local area network that uses the same protocol (for example, Ethernet or Token Ring). You can envision a bridge as being a device that decides whether a message from you to someone else is going to the local area network in your building or to someone on the local area network in the building across the street. A bridge examines each message on a LAN, "passing" those known to be within the same LAN, and forwarding those known to be on the other interconnected LAN (or LANs).
source
In bridging networks, computer or node addresses have no specific relationship to location. For this reason, messages are sent out to every address on the network and accepted only by the intended destination node. Bridges learn which addresses are on which network and develop a learning table so that subsequent messages can be forwarded to the right network.
Bridging networks are generally always interconnected local area networks since broadcasting every message to all possible destinations would flood a larger network with unnecessary traffic. For this reason, router networks such as the Internet use a scheme that assigns addresses to nodes so that a message or packet can be forwarded only in one general direction rather than forwarded in all directions.
A bridge works at the data-link (physical network) level of a network, copying a data frame from one network to the next network along the communications path.
A bridge is sometimes combined with a router in a product called a brouter.
source
Thursday, April 10, 2008
RAM Overview
by : Christophe Catesson
There are two big categories of random access memories:
* Dynamic memories (DRAM, Dynamic Random Access Module), not very costly. They are in most cases used for the central memory of the computer
* Static memories (SRAM, Static Random Access Module), quick and expensive. SRAM is notably used for cache memories of the processor
Functioning of the random access memory
The random access memory is constituted of hundred of thousand small condensers storing charges. When it is loaded, the logical state of the condenser is equal to 1, otherwise it belongs to 0, what means that every condenser represents one bit of memory.
Given that condensers off-load, it is always necessary to recharge them in a space of regular time called cycle of refreshment. Memory DRAM requires cycles of refreshment for instance (Ns) is about 15 nanoseconds.
Every condenser is coupled with a transistor allowing to "recover « or to change the state of the condenser. These transistors are lined up in form of matrix, that is they achieve a hut memory (so called memory) by a line and a column.
So, for a memory of type DRAM, the time of access is of 60 nanoseconds (35ns of delay of cycle and 25 ns of time of latency). On a computer, the time of cycle corresponds contrary to the frequency of the clock, for instance for a computer pulsated in 200 MHz, the time of cycle is 5 ns (1 / (200*106)).
As a result a computer having a frequency well brought up and using memories the time of access of which is much longer than the time of cycle of the processor must perform cycles of wait to access to the memory. In the case of a computer pulsated in 200 MHz using memories of types DRAM (which the time of access is of 60ns), there are 11 cycles of wait as a cycle of transfer. The performances of the computer are of as much diminished as there are cycles
Formats of Random Access Memory (RAM)
There are numerous types of random access memories. These all come in the form of barrettes of memory attachable on the motherboard.
* SIMM (Single Inline Memory Module): it is about printed circuits among which one of the faces has fleas of memory. There are two types of barrettes SIMM, according to the number of connector cables (30 or 72)
* DIMM (Dual Inline Memory Modulates) are from memories 64 bits, what explains why it is not necessary to match them. Barrettes DIMM have fleas of memory on both sides of printed circuit and have also 84 connector cables on each side, what endows them with a total of 168 brooches. They have bigger dimensions than barrettes SIMM (130x25mm).
* RIMM (Rambus Inline Memory Module, conscripts also RD-RAM or DRD-RAM) are from memories 64 bits developed by the society Rambus. They have 184 brooches. These barrettes have two notches of location (détrompeurs), avoiding very risk of confusion with the previous modules. Considering their well brought up speed of transfer, barrettes RIMM have a thermal film made responsible for ameliorating the clearing up of warmth. As in the case of DIMM, there are modules of smaller size, called SO RIMM (Small Outline RIMM), intended for laptop computers. Barrettes SO RIMM include only 160 brooches.
* DRAM (Dynamic RAM, dynamic RAM) is the type of memo most spread at the beginning of the millennium. It is about a memory from which transistors are lined up in a matrix according to lines and of columns. A transistor, coupled with a condenser gives the information of a bit. 1 byte consisting of 8 bits, a barrette of memory 256 Mb DRAM will contain 256 therefore * 2^10 * 2^10 = 256 * on 1024 * on 1024 = 268 435 456 bytes = 268 435 456 * 8 = 2 147 483 648 bits = 2 147 483 648 transistors. A 256 Mb barrette has so in reality a capacity of 268 435 456 bytes, that is 268 Mb! These are memories from which the time of access is 60 ns. On the other hand, accesses memory are made in general on data lined up consecutively in memory. So the mode of access in gust (burst mode) allows to achieve the three successive data in the first one without time of additional latency.
* DRAM FPM to speed up accesses to DRAM, there is a technology, called pagination consisting in achieving data located on the same column by changing the address of the line only, what allows to avoid the repetition of the number of column between the reading of each of the lines. They speak then about DRAM FPM (Fast Page Mode). FPM allows to acquire time of access in the order of 70 - 80 nanoseconds for a frequency of functioning that can go from 25 to 33 Mhz.
* DRAM EDO (Extended Data Out, Goes out of data ameliorated sometimes also called "hyper-page") appears in 1995. The technology used with this type of memory consists in addressing the following column during the reading of the data of a column. It creates an overlapping of accesses allowing to save time on every cycle. The time of access to memory EDO is therefore about 50 - 60 nanoseconds for a frequency of functioning going 33 - 66 Mhz. So, RAM EDO, when it is used in mode gust allows to acquire cycles of form 5-2-2-2, that is a benefit of 4 cycles on the access to 4 data. As much as memory EDO did not accept the upper frequencies in 66 Mhz, it disappeared in aid of SDRAM.
* SDRAM (Synchronous DRAM, translate synchronous RAM), appeared in 1997, allows a reading of data synchronized with the bus of the card-mother, contrary to memories EDO and FPM (qualified as asynchronous) having their own clock. SDRAM allows therefore to free itself from time of wait owed to synchronization with the card-mother. This one allows to acquire a cycle in mode gust of form 5-1-1-1, that is to say benefit of 3 cycles in comparison with RAM EDO. In that way SDRAM is able of working with a cadenza going until 150 Mhz, allowing him to acquire from time of access about 10 ns.
* DR-SDRAM (Direct Rambus DRAM or else RDRAM) is a type of memory allowing to transfer data on a bus of 16 wide bits to a cadenza of 800Mhz, what confers on him a band passer-by of 1,6 Go / s. As SDRAM, this type of memory is synchronized with the clock of the bus to ameliorate exchanges of data.
* DDR-SDRAM (Double Dated Miss SDRAM) is a memory based on technology SDRAM, allowing to double the rate of transfer of SDRAM with equal frequency. Reading or writing of data in memory am accomplished on the basis of a clock. Standard memory DRAM uses a method conscript SDR (Single Data Fails) consisting in reading or writing data in every forehead going up. DDR allows to double the frequency of reading / writings, with a clock pulsated in the same frequency, by sending data in every forehead going up, as well as in every downward forehead. Memory DDR has in general a commercial appellation of type PCXXXX where "XXXX " represent the debit side in Mb / s.
* DDR2 (or DDR-II) allows to attain twice as well brought up debit sides as DDR with equal external frequency. They speak about QDR (Quadruple Dated Fail or quad-pumped) to indicate the method of reading and used writing. Memory DDR2 uses in effect two channels separated for reading and for writing, so it is able of sending or of accepting twice more data than DDR.
source
There are two big categories of random access memories:
* Dynamic memories (DRAM, Dynamic Random Access Module), not very costly. They are in most cases used for the central memory of the computer
* Static memories (SRAM, Static Random Access Module), quick and expensive. SRAM is notably used for cache memories of the processor
Functioning of the random access memory
The random access memory is constituted of hundred of thousand small condensers storing charges. When it is loaded, the logical state of the condenser is equal to 1, otherwise it belongs to 0, what means that every condenser represents one bit of memory.
Given that condensers off-load, it is always necessary to recharge them in a space of regular time called cycle of refreshment. Memory DRAM requires cycles of refreshment for instance (Ns) is about 15 nanoseconds.
Every condenser is coupled with a transistor allowing to "recover « or to change the state of the condenser. These transistors are lined up in form of matrix, that is they achieve a hut memory (so called memory) by a line and a column.
So, for a memory of type DRAM, the time of access is of 60 nanoseconds (35ns of delay of cycle and 25 ns of time of latency). On a computer, the time of cycle corresponds contrary to the frequency of the clock, for instance for a computer pulsated in 200 MHz, the time of cycle is 5 ns (1 / (200*106)).
As a result a computer having a frequency well brought up and using memories the time of access of which is much longer than the time of cycle of the processor must perform cycles of wait to access to the memory. In the case of a computer pulsated in 200 MHz using memories of types DRAM (which the time of access is of 60ns), there are 11 cycles of wait as a cycle of transfer. The performances of the computer are of as much diminished as there are cycles
Formats of Random Access Memory (RAM)
There are numerous types of random access memories. These all come in the form of barrettes of memory attachable on the motherboard.
* SIMM (Single Inline Memory Module): it is about printed circuits among which one of the faces has fleas of memory. There are two types of barrettes SIMM, according to the number of connector cables (30 or 72)
* DIMM (Dual Inline Memory Modulates) are from memories 64 bits, what explains why it is not necessary to match them. Barrettes DIMM have fleas of memory on both sides of printed circuit and have also 84 connector cables on each side, what endows them with a total of 168 brooches. They have bigger dimensions than barrettes SIMM (130x25mm).
* RIMM (Rambus Inline Memory Module, conscripts also RD-RAM or DRD-RAM) are from memories 64 bits developed by the society Rambus. They have 184 brooches. These barrettes have two notches of location (détrompeurs), avoiding very risk of confusion with the previous modules. Considering their well brought up speed of transfer, barrettes RIMM have a thermal film made responsible for ameliorating the clearing up of warmth. As in the case of DIMM, there are modules of smaller size, called SO RIMM (Small Outline RIMM), intended for laptop computers. Barrettes SO RIMM include only 160 brooches.
* DRAM (Dynamic RAM, dynamic RAM) is the type of memo most spread at the beginning of the millennium. It is about a memory from which transistors are lined up in a matrix according to lines and of columns. A transistor, coupled with a condenser gives the information of a bit. 1 byte consisting of 8 bits, a barrette of memory 256 Mb DRAM will contain 256 therefore * 2^10 * 2^10 = 256 * on 1024 * on 1024 = 268 435 456 bytes = 268 435 456 * 8 = 2 147 483 648 bits = 2 147 483 648 transistors. A 256 Mb barrette has so in reality a capacity of 268 435 456 bytes, that is 268 Mb! These are memories from which the time of access is 60 ns. On the other hand, accesses memory are made in general on data lined up consecutively in memory. So the mode of access in gust (burst mode) allows to achieve the three successive data in the first one without time of additional latency.
* DRAM FPM to speed up accesses to DRAM, there is a technology, called pagination consisting in achieving data located on the same column by changing the address of the line only, what allows to avoid the repetition of the number of column between the reading of each of the lines. They speak then about DRAM FPM (Fast Page Mode). FPM allows to acquire time of access in the order of 70 - 80 nanoseconds for a frequency of functioning that can go from 25 to 33 Mhz.
* DRAM EDO (Extended Data Out, Goes out of data ameliorated sometimes also called "hyper-page") appears in 1995. The technology used with this type of memory consists in addressing the following column during the reading of the data of a column. It creates an overlapping of accesses allowing to save time on every cycle. The time of access to memory EDO is therefore about 50 - 60 nanoseconds for a frequency of functioning going 33 - 66 Mhz. So, RAM EDO, when it is used in mode gust allows to acquire cycles of form 5-2-2-2, that is a benefit of 4 cycles on the access to 4 data. As much as memory EDO did not accept the upper frequencies in 66 Mhz, it disappeared in aid of SDRAM.
* SDRAM (Synchronous DRAM, translate synchronous RAM), appeared in 1997, allows a reading of data synchronized with the bus of the card-mother, contrary to memories EDO and FPM (qualified as asynchronous) having their own clock. SDRAM allows therefore to free itself from time of wait owed to synchronization with the card-mother. This one allows to acquire a cycle in mode gust of form 5-1-1-1, that is to say benefit of 3 cycles in comparison with RAM EDO. In that way SDRAM is able of working with a cadenza going until 150 Mhz, allowing him to acquire from time of access about 10 ns.
* DR-SDRAM (Direct Rambus DRAM or else RDRAM) is a type of memory allowing to transfer data on a bus of 16 wide bits to a cadenza of 800Mhz, what confers on him a band passer-by of 1,6 Go / s. As SDRAM, this type of memory is synchronized with the clock of the bus to ameliorate exchanges of data.
* DDR-SDRAM (Double Dated Miss SDRAM) is a memory based on technology SDRAM, allowing to double the rate of transfer of SDRAM with equal frequency. Reading or writing of data in memory am accomplished on the basis of a clock. Standard memory DRAM uses a method conscript SDR (Single Data Fails) consisting in reading or writing data in every forehead going up. DDR allows to double the frequency of reading / writings, with a clock pulsated in the same frequency, by sending data in every forehead going up, as well as in every downward forehead. Memory DDR has in general a commercial appellation of type PCXXXX where "XXXX " represent the debit side in Mb / s.
* DDR2 (or DDR-II) allows to attain twice as well brought up debit sides as DDR with equal external frequency. They speak about QDR (Quadruple Dated Fail or quad-pumped) to indicate the method of reading and used writing. Memory DDR2 uses in effect two channels separated for reading and for writing, so it is able of sending or of accepting twice more data than DDR.
source
Thursday, December 27, 2007
Cisco green plan looks beyond routers
Cisco Systems wants to turn the enterprise data network into an electricity meter.
InfoWorld InfoClipz
Using open standards, the company wants to get server and storage vendors to collect and share information about their equipment and send it to Cisco routers and switches. The data could include power consumption, operating temperature and more. It's becoming a critical job, and because the network touches all IT resources across the enterprise, data collection should happen there, according to Paul Marcoux, vice president of green engineering.
Marcoux joined Cisco from American Power Conversion only about six weeks ago after Cisco created the position to overlook energy issues across all parts of the company. Networking gear itself makes up a much smaller portion of IT power consumption than do servers or storage, but Cisco plans to go beyond just making its own products more efficient.
Power is a growing issue in datacenters as the cost of energy rises and concerns about global climate change increase. Being able to collect and analyze information about power usage is a big part of the battle and becoming more crucial in the age of virtualization, according to Marcoux. Distributing storage and processing cycles without regard for power issues is not just inefficient, it's dangerous, he said.
If virtualization software looks at a process that requires more computing power or storage space, then enlists servers or storage devices that are near to overheating or running out of power, it could send a rack of servers over the edge and shut it down, Marcoux said. For that reason, the virtualization system needs to know the power status of all the resources it may call upon, he said.
By the same token, consolidated datacenters typically serve many departments of an enterprise and consume a lot of power, but those groups generally don't have to pay for their part of the power. In fact, the electricity bill often bypasses even the IT department, going to building management instead, Marcoux said. Collecting data about the power consumed by each device, and eventually by individual transactions, would allow enterprises to bill each department for the power it uses, he said.
Software on routers and switches would collect the information and then take actions or forward it on to separate building management, energy management or virtualization control systems, Marcoux said. Given the large amount of energy data to be processed, Cisco may introduce daughtercards for its platforms to provide extra computing power, he said. He hopes the technology will be in place and collecting information in enterprises within three years.
Because datacenters contain gear from so many vendors, open standards are the only way to make such a system work, according to Cisco. Fortunately, there already are several available standards, Marcoux said. Having standards already in place will help speed up adoption, Marcoux said.
"We're not trying to reinvent the wheel, we're just trying now to utilize the wheel," Marcoux said.
Cisco's proposal would represent a whole new role for networks beyond communications, said Burton Group analyst Dave Passmore. Server vendors might go along with the plan, but Cisco can't count on smooth sailing, he said. Centralized power regulation would play a role in overall management of the datacenter, an area where Cisco is attempting to make inroads with other initiatives as well.
"Who controls virtualization in the data center is going to be the new battleground," Passmore said.
source : http://www.infoworld.com/article/07/12/24/Cisco-green-plan-looks-beyond-routers_1.html
InfoWorld InfoClipz
Using open standards, the company wants to get server and storage vendors to collect and share information about their equipment and send it to Cisco routers and switches. The data could include power consumption, operating temperature and more. It's becoming a critical job, and because the network touches all IT resources across the enterprise, data collection should happen there, according to Paul Marcoux, vice president of green engineering.
Marcoux joined Cisco from American Power Conversion only about six weeks ago after Cisco created the position to overlook energy issues across all parts of the company. Networking gear itself makes up a much smaller portion of IT power consumption than do servers or storage, but Cisco plans to go beyond just making its own products more efficient.
Power is a growing issue in datacenters as the cost of energy rises and concerns about global climate change increase. Being able to collect and analyze information about power usage is a big part of the battle and becoming more crucial in the age of virtualization, according to Marcoux. Distributing storage and processing cycles without regard for power issues is not just inefficient, it's dangerous, he said.
If virtualization software looks at a process that requires more computing power or storage space, then enlists servers or storage devices that are near to overheating or running out of power, it could send a rack of servers over the edge and shut it down, Marcoux said. For that reason, the virtualization system needs to know the power status of all the resources it may call upon, he said.
By the same token, consolidated datacenters typically serve many departments of an enterprise and consume a lot of power, but those groups generally don't have to pay for their part of the power. In fact, the electricity bill often bypasses even the IT department, going to building management instead, Marcoux said. Collecting data about the power consumed by each device, and eventually by individual transactions, would allow enterprises to bill each department for the power it uses, he said.
Software on routers and switches would collect the information and then take actions or forward it on to separate building management, energy management or virtualization control systems, Marcoux said. Given the large amount of energy data to be processed, Cisco may introduce daughtercards for its platforms to provide extra computing power, he said. He hopes the technology will be in place and collecting information in enterprises within three years.
Because datacenters contain gear from so many vendors, open standards are the only way to make such a system work, according to Cisco. Fortunately, there already are several available standards, Marcoux said. Having standards already in place will help speed up adoption, Marcoux said.
"We're not trying to reinvent the wheel, we're just trying now to utilize the wheel," Marcoux said.
Cisco's proposal would represent a whole new role for networks beyond communications, said Burton Group analyst Dave Passmore. Server vendors might go along with the plan, but Cisco can't count on smooth sailing, he said. Centralized power regulation would play a role in overall management of the datacenter, an area where Cisco is attempting to make inroads with other initiatives as well.
"Who controls virtualization in the data center is going to be the new battleground," Passmore said.
source : http://www.infoworld.com/article/07/12/24/Cisco-green-plan-looks-beyond-routers_1.html
Monday, October 8, 2007
Playstation 3 New Face
Introduction
Lagging a full year behind the release of Microsoft's Xbox 360 and lacking the immediately attention-grabbing hook of Nintendo's 360-degree motion-sensing Wii, Sony's long-awaited PlayStation 3 has recently been the subject of much heated debate. Despite its obvious appeal to diehard gamers and fans of the world's most popular console brand – not to mention home theater enthusiasts, what with 1080p HDMI output and extensive online music/video download capabilities – questions have been plentiful.
For example: Is the system, available in 20GB ($499, sans WiFi and a built-in combination Memory Stick product lineup, Compact Flash and SD/MMC card reader) or $599 chrome-trimmed wireless-ready 60GB hard drive models, worth the hefty asking price, the highest since early-'90s systems like CDi and 3DO? Can Sony, who's recently cut back North American November 17th launch date ship projections to just 400,000 units (with some analysts predicting actual distribution of half this number or fewer machines), manage to avoid aggravating a soon-to-be-device-deprived buying public while still keeping up with the competition? And, of course, with so much power and hardware combined in a single unit catered to the highest-end luxury users, is there even a point to upgrading?
The short answer to all: Yes, depending which of school of thought you fall into, your game playing habits and how much disposable income you've got to burn. However, let's get one thing out of the way up-front, before you freeze your poor behind off spending all night camped out in front of the local electronics retailer hoping to score one of the severely under-stocked devices. For a host of reasons ranging from technical niggles to launch lineup shortfalls to pure common sense, it's perfectly fine – and in most cases, even advisable – to skip buying one this holiday season and wait until the dust settles sometime early in 2007.
Right from the get-go, it's important to consider the following fact: You're not actually buying a videogame console here (although surely, that's the machine's strength and the chief function most prospective buyers intend to employ it towards) so much as a full-fledged digital media hub. As slick as everything from cutting-edge digital diversions and Blu-ray movies – video resolutions ranging all the way from 480i up to an eye-popping 1080p are supported – it's what you personally make of the machine that gives the gizmo its true value. So for all of you who've been pestered since, oh, 2004 by your wide-eyed little pride and joys, remember: Dropping $599 just so kids can use the beast as an overgrown Atari may be a little much. They'll be just as entertained by lower-resolution outings for other systems like Nintendo's Wii or Sony's own PlayStation 2. And, in truth, most PlayStation 3 titles right now are simply enhanced ports of existing products anyway (see offerings like Tony Hawk's Project 8 or NHL 2K7). What's more, unless you plan on clocking in time behind the controller yourself, investing in a library of next-generation movies, browsing the Web on your TV, purchasing extra levels/cars/characters/songs/films online or are intent on building the ultimate technophile's living room setup, it's the sort of holiday gift that may be little extravagant for anyone younger than 15.
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